For more than three decades, the continued miniaturization of MOSFETs has driven the worldwide semiconductor industry. Various showstoppers to continue scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits.
Since it has become increasingly difficult to improve MOSFETs and therefore CMOS performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. CMOS scaling has been mainly driven by stress induced carrier mobility enhancement since 90 nm technology node. Increased carrier mobility can be obtained, for example, by introducing the appropriate stress/strain into the semiconductor lattice.
The application of stress changes the lattice dimensions of the semiconductor substrate. By changing the lattice dimensions, the electronic band structure of the material is changed as well. The change may only be slight in intrinsic semiconductors resulting in only a small change in resistance, but when the semiconducting material is doped, i.e., n-type, and partially ionized, a very small change in the energy bands can cause a large percentage change in the energy difference between the impurity levels and the band edge. This results in changes in carrier transport properties, which can be dramatic in certain cases. The application of physical stress (tensile or compressive) can be farther used to enhance the performance of devices fabricated on the semiconductor substrates.
Compressive strain along the device channel increases drive current in p-type field effect transistors (pFETs) and decreases drive current in n-type field effect transistors (nFETs). Tensile strain along the device channel increases drive current in nFETs and decreases drive current in pFETs.
Stress can be introduced into a single crystal oriented substrate by several methods including, for example, forming a stress liner on top of the substrate and around the gate region. Depending on the conductivity type of the FET (i.e., p or n), the stress liner can be under tensile stress (preferred for nFETs) or compressive stress (preferred for pFETs).
In order to enhance MOSFET performance in the 65 nm technology node and below, stress liners are applied after salicide formation. The liner stress is transferred to the device channel thereby enhancing the carrier mobility. In MOSFETs, there is normally a nitride or oxide/nitride spacer(s) that is used to offset the source/drain dopant from channel, and to prevent silicide from shorting to gate and from punching through the shallow extension region. The stress transfer from liner to MOSFET channel is limited by the existence of the spacer due to proximity effects.
Accordingly, there are continuing efforts to enhance stress in semiconductor devices and thus achieve greater carrier mobility and ultimately greater device performance.